The invention relates to the field of integrated circuits and in particular to an electrostatic discharge protective circuit.
Integrated circuits are becoming increasingly complex. They often contain separate components or sections that have their own voltage/power supply. In other words, out of at least two sections that form a first and second section of the circuit, each of the sections has its own separate working voltage system with ground as a fundamental voltage and a supply voltage. In order to transfer information, the two sections are linked by at least one connection. In other words, there exists one connection between an information terminal of the first section and an information terminal of the second section to transfer information between the first and the second sections.
In the event of electrostatic discharges potential differences occur between the sections or components that may destroy the structures of the circuit, in particular, through the connection between the information terminals. With increasing miniaturization of the design, the circuits become increasingly more sensitive to electrostatic discharges.
FIG. 5 illustrates, as an example, a segment of a crystal 1 of a circuit, where two sections A, B are located in an integrated circuit. The two sections A, B must be separated to the largest degree possible in order to prevent, for example, mutual interference effects. Nevertheless, signals or information must be exchanged between sections A, B. The signals are provided at corresponding information terminals, and in the case of a CMOS-based design originate in inverters or inverter-like structures such as a NAND gate or linear amplifiers. Typically, the signals are applied to the gates or control terminals of the MOS transistors of the respective other section B, A. If the voltage system, consisting of a supply voltage UDD and a ground or fundamental voltage USS of the first section A opposing the voltage system consisting of supply voltage UDD and fundamental voltage USS1 of the second section B, is now shifted in potential by an electrostatic discharge of destructive effect (i.e., by an ESD event) the potential difference is immediately transmitted through the transmission lines of connection SC on the substrate 1 to the gates of the MOS transistors of the other section. Within a few nanoseconds, these break down and are destroyed. In view of the fact that typical ESD events are in the KV or A range, whereas the gate oxides typically withstand only 6 volts for about 100 ns, it is immediately evident that such an arrangement is unsuitable.
FIG. 6 illustrates a prior art circuit having protection against electrostatic destruction. The circuit includes the first and second sections A, B, each with an applied supply voltage UDD or UDD1 and a fundamental voltage USS or USS1, respectively. The circuit also includes coupling elements KP that are connected between the two connection lines of the supply voltages UDD, UDD1 of the first and second sections A, B. Additional coupling elements KP are connected between the connection lines of the fundamental voltage USS, USS1 of the first and second sections A, B. The purpose of the coupling elements KP is to prevent or limit the potential differences of the working voltage system UDD-USS of the first section relative to the working voltage system UDD1-USS1 of the second section B. Various components are employed as coupling elements—for example, resistances, even the always present substrate resistance of an integrated circuit, diodes, bipolar transistors, or MOS transistor devices. In this configuration, the coupling elements are connected directly between the two working voltage systems of the two sections A, B. The connections SC to transfer information are formed separately.
This type of configuration is usable only to a limited extent since the coupling can be implemented only weakly, otherwise the isolation of the two sections A, B would be negated and disturbances would propagate through the lines and connections of the voltage supply. The coupling is especially problematic when the working voltage system UDD1-USS1 of the second section B has a different rated voltage than the working voltage system UDD-USS of the first section A. The constant flow of equalizing currents must be prevented. In light of these factors, the coupling elements or couplers often become quite ineffective, with the result that destructive actions continue to occur in response to electrostatic discharges. In the case of, for example, a coupler with a dynamic resistance of 10 Ohms, an ESD equalizing current of 1 A and a voltage difference of 10V between the working voltage systems of the sections A, B are sufficient to bring about immediate destruction of the gate oxides at the transitions of the first section A to the second section B, or visa versa.
Typical electronic systems on chips (SoC) currently have three or more separate components or sections with different rated voltages, with the result that the task of decoupling to prevent damage from electrostatic discharges is made that much more difficult. An additional number of couplers is required, such that the metal tracks that link these couplers generate an additional resistance within the coupling path. In parallel with this, the 100-ns breakdown voltages of the thin oxides continue to drop from one technology generation to the next. The measures used in the circuit of FIG. 6 are thus incapable of preventing damage by electrostatic discharges.
FIG. 7 illustrates a simplified technique of transferring information through a connection SC from an inverter IA2 in the first section A to an inverter IB2 in the second section B. Two diodes D1S, D2S are connected to a connection point OS at the input of the inverter IB2 of the second section B. The first diode D1S is connected between the node or connection point and the supply voltage UDD1 of the second section. The second of the diodes D2S is connected between the fundamental voltage USS1 and the connection point OS. The diodes D1S, D2S which are attached locally to the working voltage system of the second section B, limit the voltage at the inverter IB2 of the second section B. A resistance RS, which is connected between the output of the inverter IA2 and the connection point OS limits the equalizing current. The diodes D1S, D2S may also be in the form of parasitics of an MOS structure. This circuit together with the couplers of FIG. 6 provides protection from destruction by electrostatic discharges. However, the working voltage systems of the two sections A, B are no longer independent of each other. Working voltage system UDD1-USS1 of the second section B cannot, for example have a lower rated voltage than the working voltage system UDD-USS of the first section A, since otherwise in the accumulated number of inverters and resistances, significant equalizing currents would flow. Switching off the working voltage system UDD1-USS1 of the second section B is also hardly feasible. While this circuit functions in principle, it is nevertheless unsuited for the requirements of many systems.
Therefore, there is a need for improved protection against electrostatic destruction between two sections, each of which has its own working voltage system.